XJTU-ICS Textbook
Course Notes
1.
Overview
1.1.
Why ICS
1.2.
How to Start
1.3.
Coding is All You Need
2.
Representing and Manipulating Information
2.1.
Information Storage
2.2.
Integer Representations
2.3.
Integer Arithmetic
3.
Machine-Level Representation of Programs
3.1.
A Historical Perspective
3.2.
Program Encodings
3.3.
Data Formats
3.4.
Accessing Information
3.5.
Arithmetic and Logical Operations
3.6.
Control
3.7.
Procedures
3.8.
Array Allocation and Access
3.9.
Heterogeneous Data Structures
3.10.
Advanced Topic
4.
Processor Architecture
4.1.
TheY86-64 Instruction Set Architecture
4.2.
Logic Design and the Hardware Control Language HCL
4.3.
Sequential Y86-64 Implementations
4.4.
General Principles of Pipelining
4.5.
Pipelined Y86-64 Implementations
4.6.
Summary
5.
Optimizing Program Performance
5.1.
Capabilities and Limitations of Optimizing Compilers
5.2.
Optimization Blocker
5.3.
Understanding Modern Processors
5.4.
Instruction-Level Parallelism
5.5.
Branch Predictions
6.
The Memory Hierarchy
6.1.
Storage Technologies
6.2.
Locality
6.3.
The Memory Hierarchy
6.4.
Cache Memories
6.5.
The Impact of Caches on Program Performance
7.
Linking
7.1.
Base Concepts
7.2.
Procedures
7.3.
Libraries
8.
Exceptional Control Flow
8.1.
Exceptions
8.2.
Processes
8.3.
Process Control
8.4.
Signals
Dev Ops
9.
Develop Ops
9.1.
How to Use VSCode
9.2.
Windows? Linux!
9.3.
VSCode? Vim!
9.4.
G__hub? Github!
9.5.
SSH: She’s Settled for Him
9.6.
Git: Girlfriend Is Tricky
9.7.
Google Style Guide
Contributors
Light
Rust
Coal
Navy
Ayu
Introduction to Computer System
Chapter 4.2 Logic Design and the Hardware Control Language HCL
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